Electrical Characteristics
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
23-5
23.3
AC Electrical Specifications
NOTE
AC timing specifications may be subject to change during ongoing
qualification.
AC timing specifications assume maximum output load capacitance on all
output pins including SDCLK. If this value is different, the input and output
timing specifications would need to be adjusted to match the clock load.
AC timing specifications referenced to SDCLK assume SDRAM control
register bit 3 is 0. After reset this bit is set.
23.3.1
Clock Input and Output Timing Specifications
Figure 23-1. Clock Input Timing Diagram
Table 23-6. Clock Input and Output Timing Specifications
Name
Characteristic
0–66 MHz
Unit
Min
Max
Frequency of operation
0
66.00
MHz
C1
CLKIN period (T) 1
1 The clock period is referred to as T in the electrical specifications. The time for T is always in nS. Timing specifications can be
given in terms of T. For example, 2T+5 nS
15
—
nS
C2 2
2 Specification values are not tested.
CLKIN fall time (from Vh = 2.4 V to Vl = 0.5 V)
—
2
nS
CLKIN rise time (from Vl = 0.5 V to Vh = 2.4 V)
—
2
nS
C4
CLKIN duty cycle (measured at 1.5 V)
45
55
%
C4a3
3 Specification values listed are for maximum frequency of operation.
CLKIN pulse-width high (measured at 1.5 V)
6.75
8.25
nS
CLKIN pulse-width low (measured at 1.5 V)
6.75
8.25
nS
CLKIN
C1
C4a
C4b
C3
C2
Vh
Vl
(input)