Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
19-21
NOTE
In 16-bit bus mode, longword accesses are performed as two sequential
word accesses.
Table 19-6 shows how BS[3:0] should be connected to DQMx for 16- and 32-bit SDRAM configurations.
19.6.3
Read/Write (R/W)
R/W is programmed on a per-chip-select basis for use with SRAM and external peripheral write accesses.
It should be connected to the external peripheral or memory write enable signal.
R/W acts as a write strobe to external SRAM when the decoded chip select is configured for either of the
two SRAM/ROM modes. It is asserted during on-chip peripherals accesses and negated during on-chip
SRAM accesses.
Table 19-4. Byte Strobe Operation
for 16-Bit Data Bus—SRAM Cycles
BS1
BS0
Access Size
Data Located On
1
None
—
1
0
Byte
D[31:24]
0
1
Byte
D[23:16]
0
Word
D[31:16]
Table 19-5. Byte Strobe Operation
for 16-Bit Data Bus—SDRAM Cycles
BS3
BS2 Access Type Data Located On
1
None
—
1
0
Byte
D[23:16]
0
1
Byte
D[31:24]
0
Word
D[31:16]
Table 19-6. Connecting BS[3:0] to DQMx
5272
SDRAM
Data Signals
16 Bit
32 Bit
16 Bit
32 Bit (2 x 16)
32 Bit (1 x 32)
BS3
DQMH
DQM3
D[31:24]
BS2
DQML
DQM2
D[23:16]
NC
BS1
NC
DQMH
DQM1
D[15:8]
NC
BS0
NC
DQML
DQM0
D[7:0]