![](http://datasheet.mmic.net.cn/290000/XPC801ZP25_datasheet_16187868/XPC801ZP25_599.png)
Index
Index-8
MPC801
USER’S MANUAL
MOTOROLA
INDEX
N
no access override mode,
11-3
no override mode,
11-3
noise immunity,
16-5
nonmaskable interrupt (NMI),
12-5
nonoptional instructions,
7-1
O
OE,
2-5
OnCE,
1-1
OP0,
13-25
OP1,
13-25
OP2,
13-25
OP3,
13-25
operand placement (effects),
7-4
operand representation (illustration),
13-25
operation
bus,
13-8
data cache,
10-7
endian mode,
14-5
global (boot) chip-select,
15-15
nonscan chain,
19-19
operations of the data cache,
10-3
operations that support endian modes,
14-2
option register,
15-72
,
B-28
optional instructions,
7-1
OR,
15-6
ordering information,
22-1
organization, data cache,
10-2
P
package dimensions,
22-3
page size,
11-2
parallel I/O port, 16-35
features,
16-35
port B pin functions,
16-35
port B registers,
16-37
parity checking,
15-7
parity errors,
16-4
parity generation,
15-7
PB(16),
2-8
PB(17),
2-8
PB(18),
2-8
PB(19),
2-8
PB(20),
2-8
PB(21),
2-8
PB(22),
2-8
PB(23),
2-8
PB(24),
2-8
PB(25),
2-8
PB(26),
2-8
PB(27),
2-8
PB(28),
2-8
PB(29),
2-8
PB(30),
2-7
PB(31),
2-7
PBDAT,
16-37
PBDIR,
16-38
PBODR,
16-37
PBPAR,
16-38
PCI bridge,
14-2
performance,
9-12
periodic interrupt status and control register,
12-27
periodic interrupt timer (PIT), 12-2
,
12-12
block diagram,
12-12
periodic interrupt timer count register,
12-28
periodic interrupt timer register,
12-29
phase-lock loop,
13-8
PIE,
12-12
pin assignment, port B,
16-36
pin assignments,
2-1
,
22-2
pins
development port,
18-29
PLL,
5-12
PISCR,
12-27
PITC,
12-12
,
12-28
PITR,
12-29
pitrtclk clock,
12-11
PLL, 5-1
,
13-8
low power, and reset control register,
5-16
pins,
5-12
PLPRCR,
5-3
,
5-16
polling a channel,
16-6
polling mechanism,
16-18
polling UART,
16-6
PORESET,
2-6
Port B memory map,
3-3
,
A-9
port B pin assignment,
16-36
port B pin functions,
16-35
port size configuration,
15-7
port size device interfaces (illustration),
13-26
port width,
13-2
power
considerations,
20-2
consumption, minimizing,
9-6
,
10-8
keep alive,
5-23
management,
1-7
structure,
5-22
POWER SUPPLY (pin),
2-9
power-down wake-up,
5-1
power-on reset,
4-2
PowerPC architectural specifications,
1-1
PowerPC core,
1-5
,
7-1