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MOTOROLA
MPC801 USER’S MANUAL
11-1
11
SECTION 11
MEMORY MANAGEMENT UNIT
The MPC801 implements a virtual memory management scheme that provides cache
control, storage access protection, and effective to real address translation. This
implementation includes separate instruction and data memory management units. The
MPC801 memory management unit (MMU) is compliant with the
Family: The Programming Environment
in relation to the supported types of attributes,
except that two new modes of operation have been added:
PowerPC
Microprocessor
PowerPC mode with extended encoding
Domain manager mode
Available protection granularity sizes are page (4K, 16K, 512K, or 8M) or 1K subpage, the
latter of which is only supported by 4K pages. Hereafter, the prefix M
an memory management unit control register name corresponds to both the MI_ and MD_
conditions.
x
_ that appears before
11.1 FEATURES
The following is a list of the memory management unit’s main features:
8-Entry Fully Associative Data and Instruction Translation Lookaside Buffers (TLBs)
Multiple Page Sizes
High Performance
Supports Up to 16 Virtual Address Spaces
Supports 16 Access Protection Groups
Each Entry Can be Programmed to Match Problem Accesses, Privileged Accesses,
or Both.
Generates Implementation Specific Interrupts
Software Tablewalk Update Capability
MSR
IR
and MSR
DR
Control Memory Management Unit Translation and Protection
Supports PowerPC
tlbie
and
tlbia
Instructions. No
but It Is Implemented as a NOP Instruction.
Programming is Accomplished by Using the PowerPC
From the Implementation Specific Special-Purpose Registers
A Special Scratch Register is Available for Software Tablewalks
Designed for Minimal Power Consumption
tlbsync
Instruction is Supported,
mtspr/mfspr
Instructions To or