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MOTOROLA
MPC801 USER’S MANUAL
1-1
1
SECTION 1
INTRODUCTION
The MPC801 PowerPC
versatile one-chip integrated microprocessor and peripheral combination that can be used
in a variety of controller applications. It is a low-cost version of the MPC860 that provides an
effective price/performance solution across a wide range of applications. The MPC801, like
the MPC860, combines a high-performance PowerPC core with a multifaceted system
integration package. Unless otherwise specified, the PowerQUICC unit will be referred to as
the MPC801 in this manual.
Quad Integrated Communications Controller (PowerQUICC) is a
The MPC801 is a PowerPC-based derivative of Motorola’s MC68360 Quad Integrated
Communications Controller (QUICC
). The CPU on the MPC801 is a 32-bit PowerPC
implementation that incorporates memory management units and instruction and data
caches. The memory controller has been enhanced, thus enabling the MPC801 to support
any type of memory, including high performance memories and newer dynamic random
access memories (DRAMs).
The purpose of this manual is to describe the operation of all the MPC801 functionality with
concentration on the I/O functions. Additional details on the MPC801 can be found in the
PowerPC
architectural specifications.
1.1 FEATURES
The following list summarizes the main features of the MPC801:
PowerPC Single-Issue Integer Core Performs Branch Folding and Prediction with
Conditional Prefetch, but Without Conditional Execution
Precise Exception Model
Extensive System Development Support
— On-chip watchpoints and breakpoints
— Program flow tracking
— On-chip emulation (OnCE) development interface
High Performance (52K Dhrystone 2.1 MIPS @40MHz, 3.3V, 1.3W Total Power)
Low Power (3.3V Operation with 5V TTL Compatibility)
MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus
Monitor, and Real-Time Clocks
Fully Static Design (0-40MHz Operation)