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The PowerPC Core
MOTOROLA
MPC801 USER’S MANUAL
6-31
6
6.5.13 Exception Processing
An exception is a special condition that preempts normal processing. Exception processing
is the transition from normal mode program execution to the execution of a routine that deals
with an exception.
6.5.13.1 USING DAR, DSISR, AND BAR
The load/store unit keeps track of all instructions and bus cycles. When a bus error occurs,
the data address register (DAR) is loaded with the cycle’s effective address. With a
multicycle instruction, the effective address of the first offending cycle is loaded.
The data/storage interrupt status register (DSISR) notifies the error when an exception is
caused by the load/store. When a memory management unit error occurs, this register is
loaded with the error status delivered by the memory management unit. With other
exceptions, the DSISR is loaded with the instruction information as defined by the PowerPC
architecture for alignment exception. The breakpoint address register (BAR) notifies the
address on which an L-bus breakpoint occurred. For a multicycle instruction, the BAR
contains the address of the first cycle with which the breakpoint condition was associated.
The BAR has a valid value only when a data breakpoint interrupt is taken. At any other time,
its value is boundedly undefined. The following cases cause the DAR, BAR and DSISR to
be updated.
Table 6-14. DAR, BAR, and DSISR Value Summary
INTERRUPT TYPE
DAR VALUE
DSISR VALUE
BAR VALUE
Data Storage Interrupt
Cycle EA
MMU Error Status
Undefined
Alignment Interrupt
Data EA
Instruction Information
Undefined
L-Bus Breakpoint Interrupt
Does Not Change
Does Not Change
Cycle EA
Machine Check Interrupt
Cycle EA
Instruction Information
Undefined
Implementation Dependent
Software Emulation Interrupt
Does Not Change
Does Not Change
Undefined
Floating-Point
Unavailable Interrupt
Does Not Change
Does Not Change
Undefined
Program Interrupt
Does Not Change
Does Not Change
Does Not Change