![](http://datasheet.mmic.net.cn/290000/XPC801ZP25_datasheet_16187868/XPC801ZP25_226.png)
System Interface Unit
MOTOROLA
MPC801 USER’S MANUAL
12-19
12
FRC—FRZ Pin Configuration
This bit configures the functionality of the FRZ/IRQ6
pin.
0 = FRZ/IRQ6 functions as FRZ.
1 = FRZ/IRQ6 functions as IRQ6.
DLK—Debug Register Lock
If this bit is set (1), bits 8–15 are locked and writes to those bits can no longer be performed.
Bits 8–15 can be written in test mode once the internal freeze is asserted, regardless of the
state of DLK. This bit is cleared by reset.
OPAR—Odd Parity
This bit is used to program odd or even parity. It can also be used to generate parity errors
for testing purposes by writing the memory with OPAR = 1 and reading the memory with
OPAR = 0.
PNCS—Parity Enable For Nonmemory Controller Regions
This bit enables parity generation/checking for memory regions not controlled by the
memory controller.
DPC—Data Parity Pins Configuration
This bit configures the functionality of the DP[0:3]/IRQ[3:6]
pins.
0 = DP[0:3]/IRQ[3:6] functions as IRQ[3:6].
1 = DP[0:3]/IRQ[3:6] functions as DP[0:3].
MPRE—Multiprocessors Reservation Enable
This bit configures the functionality of the RSV/IRQ2 and CR/IRQ3 pins.
0 = RSV/IRQ2 and CR/IRQ3 function as RSV and CR accordingly. Reservation
protocol is enabled.
1 = RSV/IRQ2 and CR/IRQ3 function as IRQ2 and IRQ3 accordingly. Reservation
protocol is disabled.
MLRC—Multi-Level Reservation Control
This bit configures the functionality of the KR/IRQ4 pins.
00 = KR/IRQ4 functions as IRQ4.
01 = Reserved.
10 = KR/RETRY/IRQ4 functions as KR/RETRY.
11 = Reserved.
AEME—Asynchronous External Master Enable
This bit configures how the memory controller refers to external asynchronous masters
initiating a transaction. If this bit is set, the memory controller interprets any assertion on the
AS pin as an external asynchronous master initiating a transaction. If it is reset, the memory
controller ignores the value of the AS pin.