![](http://datasheet.mmic.net.cn/290000/XPC801ZP25_datasheet_16187868/XPC801ZP25_130.png)
PowerPC Architecture Compliance
MOTOROLA
MPC801 USER’S MANUAL
7-7
7
7.3.2.1.2 Added Registers.
For a list of the added special-purpose registers, see
Table 6-9.
7.3.3 Storage Model
Page sizes are 4K, 16K, 512K, and 8M and an optional sub-page granularity of 1K for 4K
pages comes to a maximum real memory size of 4G. Neither ordinary or direct-store
segments are supported.
7.3.3.1 ADDRESS TRANSLATION
If address translation is disabled (MSR
IR
=0 for instruction accesses or MSR
DR
=0 for data
accesses), the effective address is treated as the real address and is passed directly to the
memory subsystem. Otherwise, the effective address is translated by using the translation
lookaside buffer (TLB) mechanism of the memory management unit. Instructions are not
fetched from no-execute or guarded storage and data accesses are not executed
speculatively to or from the guarded storage. The features of the memory management unit
hardware is as follows:
32-entry fully associative instruction TLB
32-entry fully associative data TLB
Supports up to 16 virtual address spaces
Supports 16 access protection groups
Supports fast software tablewalk mechanism
7.3.4 Reference and Change Bits
No reference bit is supported by the MPC801. However, the change bit is supported by
using the data TLB error interrupt mechanism when writing to an unmodified page.
7.3.5 Storage Protection
Two main protection modes are supported by the MPC801:
Domain manager mode
PowerPC mode
For more details, refer to
Section 11 Memory Management Unit
.
7.3.6 Storage Control Instructions
7.3.6.1 DATA CACHE BLOCK INVALIDATE (dcbi)
This instruction is executed according to the definition in PowerPC
Operating Environment
Architecture Book III
7.3.6.2 TLB INVALIDATE ENTRY (tlbie)
This instruction is performed as defined by the architecture, except that the 22
most-significant bits of the EA are used for address compare.