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Applications
MOTOROLA
MPC801 USER’S MANUAL
B-11
B
The following table shows the tasks that can be performed using the memory management
unit.
Table B-7. Physical Memory Map Example
ADDRESS RANGE
00000000 - 003FFFFF
00400000 - 007FFFFF
00800000 - 00BFFFFF
09000000 - 09003FFF
09100000 - 09100003
10000000 - 17FFFFFF
NOTE:
1.
ACCESSED DEVICE
FLASH PROM Bank 1
FLASH PROM Bank 2
DRAM 4MByte (4 Meg X 32bit)
MPC Internal MAP
Board Control & Status Register (BCSR)
PCMCIA channel
PORT WIDTH
32
32
32
32
32
16
Configured at hard reset via the hard reset configuration word to FF000000, changed during a special register,
and written/read using
mtspr
/
mftspr
commands.
2.
The BCSR is available throughout the minimal block size of the MPC801’s CS region, which is 64K.
(091000000–0910FFFF).
Table B-8. MMU Register
EFFECTIVE ADDRESS=
REAL ADDRESS
PAGE SIZE/
NO. OF
PAGE
8M/1
CACHE/
GUARD
CACHE
MODE
ACCESS
PRIVILEGE
READ/
WRITE
SHARED
PAGE
NOTE
00000000 - 007FFFFF
On/No
Writethrough
Privilege
Read-only
Shared
Used for monitor
program and
translation table
Used for stack and
monitor scratch pad.
Used for data buffers
Used for problem
program and data
space
Used to access
Power QUICC
internal RAM and
registers
Used for access to
board configuration
register.
00800000 - 008FFFFF
512K/2
On/No
Copyback
Privilege
Read/Write
Shared
00900000 - 0094FFFF
00950000 - 00BFFFFF
512K/1
512K/5
Off/Yes
On/No
—
Privilege
Privilege/
Problem
Read/Write
Read/Write
Shared
Shared
Copyback
09000000 - 09003FFF
16K/1
Off/Yes
—
Privilege
Read/Write
Shared
09100000 - 09103FFF
16K/1
Off/Yes
—
Privilege
Read/Write
Shared
10000000 - 17FFFFFF
NOTE: The above cache and protection mode is selected to show as many of the variations as possible. There is no reason why some pages
are selected as copyback or some writethrough other than for showing how this selection can be made.
8M/16
Off/Yes
—
Privilege
Read/Write
Shared