參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 92/172頁
文件大?。?/td> 1142K
代理商: LR4500
5-22
Bus Interface Descriptions
5.2.3 CW4011 Shell Reset/Interrupt Interface
Figure 5.8
shows the internal interface that links the CW4011 shell, the
SCLC, and the DRAMC to provide the reset and interrupt signals
required by CP0.
Figure 5.8 Shell Reset/Interrupt Interface
BENDn
Big Endian (Strap Input)
This input affects the byte positions for sizing and
load/store data alignment. When the input is LOW
(asserted), the CW4011 works with big endian byte
ordering. When HIGH, byte ordering is little endian.
Input to Shell
EXVAp[31:2]
External Vectored Interrupt Address
Input to Shell from SCLC
The CW4011 shell accepts the external vectored interrupt
address when the SCLC asserts EXVApEn. The CW4011
writes the address directly into the program counter. The
address bus must remain stable until EXVApEn is
asserted.
CW4011
Shell
SEXINT[5:0]
SNMin
SWRESETn
SCRESETn
Pin Inputs
SCbus/Lbus
Converter
DRAM
Controller
FRCMn
BENDn
EXViNTn
EXVAp[31:2]
EXVAEn
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