參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 135/172頁
文件大?。?/td> 1142K
代理商: LR4500
ICEport Functional Blocks
9-3
9.3 ICEport Functional Blocks
The CW4011 ICEport design has been partitioned into three logical
blocks:
Receive and Transmit logic block that sends and receives the
ICETXp and ICERXp signals.
The Generic Interface logic block, common to most core designs,
that implement a SerialICE ICEport.
The SCbus Interface logic block that connects the ICEport with the
rest of the CW4011 core by means of SCbus signals.
Figure 9.2
shows how these blocks interact with each other and interface
to other core logic and external logic.
Figure 9.2 ICEport Block Diagram
SCBUS
ICERXp
ICETXp
ICECLKp
sc_ICEDip[7:0]
sc_ICEDop[31:0]
SCLKp
SCLKp
IRXRDYp
Operation
CRESETn
WRESETn
SCAop[31:0]
SCDoEn
SCTSSn
sc_ICERDYp
sc_ICEDoEp
SCbus Glue Logic
Generic
Interface
Receive
Rx
Transmit
Tx
ICEport
Select
Read/Write
Ready
Generation
Address
Decode
Control
sc_ICEINTp
ICEport
Building
Block
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