參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 154/172頁
文件大?。?/td> 1142K
代理商: LR4500
9-22
ICEport
The UART receiving the output from ICETXp may, however, require less
difference between the two frequencies, and this requirement must be
observed.
The ICECLKp signal may be derived from SCLKp by using a divider. This
method frees a pin since ICECLKp no longer requires an external pin.
The operation of the ICEport does not change in any way if ICECLKp is
derived from SCLKp, but the frequency difference of
±
1% must be
adhered to regardless of the clock rate.
The ICEport may also transfer data internally between the two clock
domains (between ICEport and the core). For these transactions, the
ICECLKp frequency can be at most one quarter of the SCLKp frequency.
No matter what the frequency difference between ICECLKp and SCLKp,
the bus master must have enough time to read received data before new
data arrives, otherwise, an overrun error will occur.
9.7 ICEport Pin Buffers and Drivers
The choice of ICEport external pin buffers and drivers will vary with each
design. However, this section provides a few general recommendations
for any design using an ICEport. Please note that the pin reserved for
ICECLKp may be conserved if the ICEport clock is internally derived from
SCLKp, as described in
Section 9.6.5, “Clock Domains and Properties.”.
The buffer for input pin ICERXp should be a 5 V-compatible schmitt
trigger with an internal pull-up resistor, since the incoming signal may
be noisy and driven from a 5 V source. An internal pull-up resistor is
recommended so that ICERXp can be left unconnected if the
ICEport is unused.
The driver for the ICETXp output pin should be a 4 mA driver, with
a reduced slew rate to avoid reflections.
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