參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 106/172頁
文件大小: 1142K
代理商: LR4500
6-12
DRAM Controller and Memory Bus
Bits [21:20] in the DRAM Controller Configuration
Register also select the cycle modes. You must set or
clear the bits in both registers, as described in
CL CAS
Latency [21:20]
on
page 6-6
, to select the required mode.
WT
Wrap Type
Sequential mode is compatible with SCbus burst order-
ing. Since burst length is one word for the LR4500, wrap
type is not used in the LR4500, so you should clear this
bit to 0 to enable sequential accesses. Setting the bit to
1 enables interleaved accesses.
3
BL
Burst Length
You can select single-cycle mode by clearing bits [2:0] of
this register to 0b000. The SCbus requests four double-
words as a burst block. With a data bus width of 64 bits,
the LR4500 supports the request with multiple CAS
accesses.
[2:0]
6.6 DRAM Refresh
The DRAM Controller needs to refresh the 2048 rows in the synchronous
DRAM every 32 milliseconds. The controller also needs to set up a
15,625 ns (15.625
μ
s) refresh interval. For example, if the maximum
clock frequency is 66 MHz, the controller must issue a DRAM refresh
command every 1,041 clock cycles.
The DRAM Controller has an 11-bit refresh interval timer that generates
the refresh command. The refresh interval timer, shown in
Figure 6.5
,
consists of one 11-bit register, referred to as the Refresh Register, which
stores the refresh interval time; and one 11-bit binary countdown register,
referred to as the Refresh Counter, which stores the refresh counter
value, and is decremented by each system clock input. The Refresh
Register address is shown below.
Virtual Address
Physical Address
0x B000 0004
0x 1000 0004
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