參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 77/172頁
文件大?。?/td> 1142K
代理商: LR4500
External Interfaces
5-7
LADSn
Lbus Address Strobe
This signal strobes the Lbus addresses. The bus master
asserts it at the first LCLKp cycle of a transaction. When
the LR4500 asserts LHLDAp and grants bus ownership
to an Lbus master device, the master device inputs this
signal to the LR4500. When the LR4500 is the bus
master, it inputs this signal to the Lbus device. The
initiating device must synchronize this signal to the Lbus
clock, LCLKp.
Bidirectional
LBEn[3:0]
Lbus Byte Enable Signals
The master device drives these signals active (LOW), to
enable data on the Lbus, as shown below. The read/write
signal, LRDn, controls the direction of data flow. Byte
operations, that is operations where individual bytes are
selected, occur only during write transactions.
Bidirectional
LCHALFn
Lbus Clock Speed
This signal sets the clock speed for the Lbus. When a
device on the Lbus drives this signal HIGH, it divides the
SCbus clock (SCLKp) by two, and the LR4500 outputs a
clock signal (LCLKp) that is one half the frequency of
SCLKp. When the signal is LOW, it divides the SCLKp by
four, and the LR4500 outputs LCLKp at one quarter the
frequency of SCLKp.
Input
LCLKp
Lbus Clock
This output is derived from the SCbus clock, SCLKp.
Lbus clock rate is either half or quarter the clock rate of
SCLKp, depending on the state of the LCHALFn input to
the LR4500.
Output
LCRESETn
LCLK Divider Reset
LSI Logic uses this signal for testing. You can deassert
the signal by strapping it HIGH.
Input
Byte Enable Signal
Byte Bits
Byte Number
LBEn 3
LBEn 2
LBEn 1
LBEn 0
LDp[31:24]
LDp[23:16]
LDp[15:8]
LDp[7:0]
Byte 3
Byte 2
Byte 1
Byte 0
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