參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 102/172頁
文件大?。?/td> 1142K
代理商: LR4500
6-8
DRAM Controller and Memory Bus
RAS
Active to Precharge Command Period
This field allows you to select the number of clock cycles
that RAS should stay active until the memory has been
precharged. You can program the bits as follows:
[10:8]
DAL
Data In to Active/Refresh Command Period
This field allows you to select the number of active clock
cycles between the time data input is valid until the
refresh command is asserted. You can set the field as
follows:
[6:4]
RP3
Precharge to Active Command Period
This bit allows you to select the number of active clock
cycles in the period between precharge and an active
read or write command. If you set the bit to 1, there are
three clock cycles. If you clear the bit to 0, there are two
clock cycles.
1
DPL2
Data In to Precharge Command Period
This bit allows you to select the number of active clock
cycles in the period between the input of valid data to the
assertion of the precharge command. If you set the bit
to 1, there are two clock cycles. If you clear the bit to 0,
there is one clock cycle.
0
The relationship between latency and frequency varies, depending on
the DRAM specification.
Table 6.3
shows an example of the timing
parameters for three NEC DRAMS—uPD4516821, uPD4516421, and
uPD4516161 DRAMs. For the fastest access time, you should use a
Bit 10
Bit 9
Bit 8
Active RAS
Cycles
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
3
4
5
6
7
Bit 6
Bit 5
Bit 4
Active DAL
Cycles
0
1
1
1
0
0
1
0
1
3
4
5
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