參數(shù)資料
型號(hào)： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述： 超標(biāo)量微處理器（超標(biāo)量微處理器）
文件頁數(shù)： 127/172頁
文件大?。?/td> 1142K
代理商： LR4500
External Vectored Interrupt (EVInt) Support
7-9
The physical and virtual addresses for the registers are as follows:
The sections “
SCbus Error Address Register
” and
“SCbus Error Status
Register” on page 3-10
provide further information about these registers.
7.5 External Vectored Interrupt (EVInt) Support
The LR4500 has a special interrupt exception input feature called
External Vectored Interrupt. The SCLC module provides test support for
this feature with the EXVI control register shown in
Figure 7.6
.
Figure 7.6 External Vectored Interrupt Register Bit Format
The physical and virtual addresses for the register are as follows:
The section
“External Vectored Interrupt Register” on page 3-11
provides
further information about these registers.
When the LR4500 reads an exception vector address from EXVAp[31:2],
it writes the address to the program counter. The EVIA[31:2] bits in the
EXVI Register are connected to the EXVAp[31:2] bus to provide the
vector address. When the LR4500 accepts an EVInt exception, it clears
the EVIA bits to zero indicating that the timing was correct when the
CW4011 sampled EXVAp[31:2].
Register
Physical Address
Virtual Address
SCbus Error Address
SCbus Error Status
0x1010 0000
0x1010 0004
0x B010 0000
0x B010 0004
31
0
1
SEVI
EVIA[31:2]
HEVI
HEVI: Hardware External Vectored Interrupt
SEVI: Software External Vectored Interrupt
2
Register
Physical Address
Virtual Address
External Vectored Interrupt
0x1010 0008
0x B010 0008
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