參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 29/172頁
文件大?。?/td> 1142K
代理商: LR4500
System Configuration
3-5
3.3 System Configuration
LR4500 has a number of features that allow you to modify the system
configuration. This section describes the Configuration and Cache
Control (CCC) Register, which is part of the CW4011 core, and several
Lbus registers, which are part of the SCLC module. You can also
configure the DRAM, as described in
Chapter 6
, “
DRAM Controller and
Memory Bus
.”
3.3.1 CCC Register
The Configuration and Cache Control (CCC) Register is part of CP0, the
system coprocessor. The CCC Register allows you to use software to
configure various pieces of the core design, such as the Bus Interface
Unit (BIU) and the controllers for the I-cache and D-cache.
You can read from the CCC Register using the MFC0 instruction, and
write to it using the MTC0 instruction.
Table 4.14 on page 4-14
describes
these instructions. The register’s address in CP0 is ‘16.’
Figure 3.2
shows
the bit configuration of the CCC Register. All bits are initialized to 0 at
reset, so that the caches are not available until the register is
programmed.
Figure 3.2 CCC Register
R
Reserved
This field is reserved. The bits are cleared to 0.
[31:29]
EWP
External Write Priority
This bit defines the arbitration priority on the SCbus
between a data read and data write transaction in the
28
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
EWP SDB
IR1
EVI
CMP
IIE
DIE
MUL
MAD
TMR
BGE
IE0
IE1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IS[1:0]
DE0
DE1
DS[1:0]
IPWE
IPWS[1:0]
TE
WB
SR0
SR1
IsC
TAG
INV
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