參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 105/172頁
文件大小: 1142K
代理商: LR4500
DRAM Mode Register
6-11
CAS Latency
Defines the number of clock cycles that must occur before data is
available.
Auto Precharge
This mode is not used in the LR4500.
Figure 6.4
shows the format of the 12-bit DRAM Mode Register. This
register is programmed by a mode write command and is located in an
SDRAM.
Figure 6.4 DRAM Mode Register Format
When you power up the DRAM, the boot program precharges the DRAM
devices. You should refer to the documentation supplied with the DRAM
for further information on precharging. After precharge, you must set the
MRS bit in the DRAM Controller Configuration Register (see
page 6-6
).
R
Reserved
These bits are not used. They are set to 0.
[11:10] [8:7]
WB
Cache Write Through and Write Back
You can select cache write through mode by setting this
bit to 1. Setting the bit to 0 selects write back mode.
However, there is no significance to write through and
write back modes in LR4500 transactions, since the burst
length is one word.
9
CL
CAS Latency
You can select among one-, two-, and three-cycle modes
by programming bits [6:4]. You should select one of the
following settings. All other settings are reserved.
[6:4]
11
10
9
8
7 6
4
3
2
0
R
WB
R
CL
WT
BL
Bit 6
Bit 5
Bit 4
Cache Latency Modes
0
0
0
0
1
1
1
0
1
1
2
3
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