參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 39/172頁
文件大小: 1142K
代理商: LR4500
Instruction Set
4-3
Table 4.2
describes the load linked MIPS II instructions.
Store Byte
SB rt, offset(base)
Sign extend the 16-bit
offset
and add to the contents of register
base
to
form address. Store least significant byte of register
rt
at addressed
location.
Store Halfword
SH rt, offset(base)
Sign extend the 16-bit
offset
and add to the contents of register
base
to
form address. Store least significant halfword of register
rt
at addressed
location.
Store Word
SW rt, offset(base)
Sign extend the 16-bit
offset
and add to the contents of register
base
to
form address. Store contents of register
rt
at addressed location.
Store Word Left
SWL rt, offset(base)
Sign extend the 16-bit
offset
and add to the contents of register
base
to
form address. Shift contents of register
rt
left so that the left most byte of
the word is in the position of the addressed byte. Store word containing
shifted bytes into word at addressed byte.
Store Word Right
SWR rt, offset(base)
Sign extend the 16-bit
offset
and add to the contents of register
base
to
form address. Shift contents of register
rt
right so that the right most byte
of the word is in the position of the addressed byte. Store word containing
shifted bytes into word at addressed byte.
Table 4.1 Load and Store Instructions (Cont.)
Instruction
Format and Description
Table 4.2 Load Linked MIPS II Instructions
Instruction
Format and Description
Load Linked
LL rt, offset(base)
Sign extend the 16-bit
offset
and add to the contents of the register
base
to form the address. Load the addressed word into register
rt
.
Store Conditional
SC rt, offset(base)
Sign extend the 16-bit
offset
and add to the contents of the register
base
to form the address. Conditionally store register
rt
at the address, based
on whether the load-link has been “broken.”
Synchronize
SYNC
Complete all outstanding load and store instructions before allowing any
new load or store instruction to start.
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