參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 134/172頁
文件大?。?/td> 1142K
代理商: LR4500
9-2
ICEport
Figure 9.1 CW4011 Design with ICEport
9.2 ICEport Features
The ICEport has the following features:
Full-duplex operation.
Requires clock support at 16 times the transfer bit rate to define
receiving (Rx) and transmitting (Tx) rates. This clock is common for
Rx and Tx, and may be either an external clock or one generated
internally from the system clock.
Rx ready signal to indicate that a byte of data has been received and
is in the data byte input buffer.
Separate status and data registers for Rx and Tx. The Rx Status
Register contains one bit that indicates received data is in the
ICEport, and one bit that indicates an overrun in the Rx input buffer.
The Tx Status Register contains one bit that indicates the ICEport is
ready to transmit data.
Serial-receive and clock input do not require an active signal when
the ICEport is unused. During reset, the Tx UART port defaults to an
idle state and transmits an idle signal.
CW4011
Core
SCbus
Rx Input
Serial Clock
Tx Output
Rx Interrupt
SCBus Control Signals
SCLC
SDRAMC
ICEport
SCBus Control Signals
Interrupt
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