參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 108/172頁
文件大?。?/td> 1142K
代理商: LR4500
6-14
DRAM Controller and Memory Bus
Table 6.4 Refresh Register Programming Values
6.7 DRAM Commands
This section describes the DRAM commands used by the LR4500 DRAM
Controller. These commands are the chip select commands (MCSn[1:0]),
row and column addresses strobes (RASn and CASn), and the write
enable command (MWEn). The DRAM Controller does not use the
DRAM’s Self-Refresh Entry Command and Burst Stop Command. In
addition, for a No Operation (Nop), the DRAM Controller deasserts the
chip select outputs MCSn[1:0] and the other control signals.
Clock
Frequency
Clock
Cycle Time
Value (A)
1
1. Value A is derived from the required refresh interval time (15,625 ns) divided by the clock cycle
time (12.5 ns, and so forth).
2. Number of clock cycles required for a burst read transaction.
3. The Refresh Register programmed values is derived from Value A minus Value B.
Number of
Clock Cycles
Required (B)
2
Refresh Register
Programmed Value
3
Decimal (Hex)
Table 6.5
shows how the Refresh Register settings are arrived at. The example shown in
the table is for the 80 MHz, 12.5 ns DRAM.
CL Setting
100 MHz
10 ns
1563
12
1551 (0x61A)
3
80 MHz
12.5 ns
1250
12
1238 (0x406)
3
66 MHz
15 ns
1041
10
1031 (0x407)
2
50 MHz
20 ns
781
8
773 (0x305)
1
Table 6.5 Refresh Register Setting for 80 MHz 12.5 ns DRAM
Register Bits
31
30
29
28
27-11
10
9
8
7
6
5
4
3
2
1
0
Binary Setting
0
0
0
0
x
1
0
0
1
1
0
1
0
1
1
0
Hex Value
0
x
4
0
6
Decimal Value
Not used
1 2 3 8
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