參數(shù)資料
型號： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述： 超標(biāo)量微處理器（超標(biāo)量微處理器）
文件頁數(shù)： 153/172頁
文件大?。?/td> 1142K
代理商： LR4500
ICEport Operations
9-21
When the Rx block receives the stop bit correctly, a LOW value in the bit
stream immediately following the stop bit will start the next frame. The
start bit must be allowed to begin quickly, since ICECLKp may be slower
than the clock that generates the data for ICERXp. In such a case, the
next received frame may start on the next sample ICECLKp.
9.6.4.2 Transmit (Tx) Block
The ICETXp signal is the ICEport serial data output and can carry new
data every 16 ICECLKp cycles. When there is no data for transmission,
ICETXp is held HIGH in an idle state. During this idle state, the TxRDY
bit in the Tx Status Register is set to one, which indicates that
transmission may be initiated by placing data in the Tx Data Register.
After data is written to the Tx Data Register, the ICEport clears the
TxRDY bit to zero.
Start bit transmission begins on the rising edge of ICECLKp and the first
data bit starts transmitting 16 ICECLKp clock cycles later. Every bit of the
transmitted frame has a width of 16 ICECLKp cycles. The Tx Data
Register LSB (bit 0) is transmitted just after the start bit; the MSB (bit 7)
is sent just before the stop bit. All data bits are transmitted true level, with
zeros sent as LOW values and ones sent as HIGH values.
The ICEport sets the TxRDY bit in the Tx Status Register when data bit 7
(the end of the byte) begins transmitting. As soon as TxRDY is set, the
next data byte to transmit can be written to the Tx Data Register. Writing
to the Tx Data Register while either data bit 7 or the stop bit is
transmitting ensures that the ICETXp signal will not be idle. If the next
data byte is not written to the Tx Data Register before the stop bit is
transmitted, the Tx block will idle for a number of ICECLKp cycles, until
new data is available in the Tx Data Register.
9.6.5 Clock Domains and Properties
Since data commonly moves between the ICECLKp domain and the Rx
clock domain, these two clocks must have frequencies within certain
limits. The difference between the ICECLKp frequency and the ICERXp
clock frequency may be no more than
±
1%, with ICERXp jitter margins
±
10% of the bit width. This jitter can originate from transmission cables
or different timing in LOW-to-HIGH and HIGH-to-LOW transitions.
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