參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 15/172頁
文件大?。?/td> 1142K
代理商: LR4500
LR4500 Features
1-3
The Lbus that allows you to plug in devices such as a Boot-ROM,
serial I/O devices, and an external Ethernet controller. (The Lbus is
a simple, generic interface for peripheral devices such as ROMs,
RAMs, UARTs. It has a demultiplexed 32-bit address bus and 32-bit
data bus, and it is similar to the 486 VLbus.)
1.2 LR4500 Features
The LR4500 Microprocessor has the following features:
System clock operating at up to 100 MHz, with 150 Dhrystone MIPS
performance
Superscalar microprocessor support for the MIPS II 32-bit instruction
set:
Up to two instructions executed per clock cycle
Four-deep write buffer
Load scheduling
R3000/R4000 compatible mode for the Exception Return and
Status Register
32-bit timer (R4000 compatible)
SCbus watchdog timer with error reporting features
Full internal SCAN testing
SerialICE debugging support provided through the ICEport UART
interface
SCbus/Lbus converter to control the Lbus and external Lbus devices
Easily implemented interface to the SONIC Ethernet controller
Synchronous DRAM Controller, with 64-bit wide data transfer,
interfaces to the following 16-Mbit SDRAMs (synchronous DRAMs):
1-M x 16-bit SDRAM devices in an 8-Mbyte or 16-Mbyte
configuration
2-M x 8-bit SDRAM devices in a 16-Mbyte or 32-Mbyte
configuration
4-M x 4-bit SDRAM devices in a 32-Mbyte or 64-Mbyte
configuration
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