參數(shù)資料
型號： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述： 超標(biāo)量微處理器（超標(biāo)量微處理器）
文件頁數(shù)： 87/172頁
文件大?。?/td> 1142K
代理商： LR4500
Internal Interface
5-17
CW4011 shell samples the signals on the rising edge of
the clock when SCBRDYn is asserted. The signals are
valid throughout a write transaction in which the CW4011
writes to DRAM through the DRAMC, or the Lbus device
writes to the CW4011 or DRAMC through the SCLC. Byte
ordering is little endian.
SCDoEn
Data Output Enable
Output from Shell to SCLC and
DRAMC
The CW4011 asserts SCDoEn throughout a write
transaction and outputs it to the SCLC or the DRAMC.
The signal indicates that the current transaction is a write
transaction, and it also enables data output. It performs
the same function for a CW4011 write transaction to
DRAM that SLWRn (
page 5-19
) performs for an SCLC
write transaction to DRAM. When TESTMp is asserted,
SCDoEn is asserted. Other data output enables must be
deasserted when TESTMp is asserted.
SCHGTn
Bus Hold Grant
The CW4011’s bus interface unit enters the hold state
and asserts SCHGTn to indicate that it is releasing
SCbus ownership in response to a bus hold request
(SCHRQn) from one of the devices on the Lbus.
Output from Shell to SCLC
SCHRQn
Bus Hold Request
SCHRQn indicates that a device on the Lbus is
requesting ownership of the SCbus. Bus hold request has
the highest priority during bus arbitration. However, it
cannot break continuous transactions of in-page writes
and burst read/write transactions if those transactions are
supported by an asserted SCTSEn. In such a case,
SCHRQn must wait until SCTSEn is deasserted.
Input to Shell from SCLC
SCLoCKn
Bus Lock
The CW4011 asserts SCLoCKn to indicate that it wishes
to lock the SCbus and restrict ownership. The CW4011
asserts the signal when a read transaction is started by
executing a Load Link instruction in an uncached area or
a write through cached area. It deasserts the signal just
before a write transaction is started by executing a Store
Conditional instruction. During read and write
transactions, the CW4011 asserts the signal
continuously, preventing ownership from changing during
one of these transactions. If a Store Conditional
Output from Shell to SCLC
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