參數資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數: 100/172頁
文件大?。?/td> 1142K
代理商: LR4500
6-6
DRAM Controller and Memory Bus
R
Reserved
These bits are not used. They should be cleared to 0.
31 [27:22] [19:18] 11, 7 [3:2]
PC
Precharge Command
This bit enables the manual precharge command. If the
CPU sets the bit to 1, the DRAM Controller generates
one precharge command cycle for both banks. The CPU
sets the bit at power up. Initialization clears the bit
automatically.
30
MRS
Mode Register Set
If the CPU sets the bit to 1, the subsequent Store Word
operation to the DRAM area generates a Mode Register
Set command. The row address bits in the SC address
bus (SCAp[22:11]) select the addressed location during
this type of operation. SCAp[31:23] and SCAp[10:0],
which are the mode bits, must be set to 0. The CPU
clears the MRS bit when the word operation has been
completed.
29
REF
Refresh Cycle
This bit enables the manual refresh cycle request (REF).
If the CPU sets it to 1, one refresh cycle is generated for
both memory banks. This bit is cleared automatically
when the refresh cycle has been completed. You can also
generate REF using the refresh counter, as described in
“DRAM Refresh” on page 6-12
.
28
CL
CAS Latency
You can set CAS Latency by programming the bits in this
field. You should select one of the following settings:
[21:20]
Although you can define all DRAM timing parameters
independently, CAS Latency defines the relationship
between other timing parameters.
Table 6.3
on
page 6-10
shows the relationships between CAS Latency, DRAM
frequency, and other configuration settings.
Bit 21
Bit 20
Cache Latency Modes
0
1
1
1
0
1
1
2
3
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