參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 35/172頁
文件大?。?/td> 1142K
代理商: LR4500
System Configuration
3-11
3.3.2.3 External Vectored Interrupt Register
The External Vectored Interrupt Register supports the LR4500 interrupt
exception feature called External Vectored Interrupt. The register’s virtual
address is 0xB010 0008 and its physical address is 0x1010 0008. For
further information about this register, refer to
“SCbus Timeout Watchdog
Timer” on page 7-8
.
Figure 3.5 External Vectored Interrupt Register
EVIA[31:2]
External Vectored Interrupt Address
This field contains the exception vector address.
[31:2]
HEVI
Hardware External Vectored Interrupt
This bit is set when the error that caused the interrupt is
a hardware error.
1
SEVI
Software External Vectored Interrupt
This bit is set when the error that caused the interrupt is
a software error.
1
31
2
1
0
EVIA[31:2]
HEVI
SEVI
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