參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 28/172頁
文件大?。?/td> 1142K
代理商: LR4500
3-4
Programming Model
3.2 Memory Mapping
Figure 3.1
shows the physical memory map of the LR4500 reference
device, where the LR4500 is master of the Lbus and an Lbus device is
slave, and the physical memory map where an Lbus device is the Lbus
master and the LR4500 is slave. In both cases, address spaces are
linear 4-Gbyte spaces. Lbus master devices cannot access LR4500
internal memory-mapped registers.
Synchronous DRAM main memory that is interfaced to the LR4500 is
located at address space 0x0000 0000 through 0x03FF FFFF. The
LR4500 works as an Lbus slave device for this 64-Mbyte memory space.
There is no guarantee that memory devices exist in the entire
64-Mbyte area. Software, in the form of a setup/bootstrap utility or
equivalent must check installed memory size when the system is
initialized. The upper 192-Mbyte space is reserved as an extended main
memory area.
LR4500 internal registers for DRAM Controller and error reporting are
located in the Internal Registers area between addresses 0x1000 0000
and 0x10FF FFFF. These registers must be accessed through kseg1 the
uncached unmapped area. The virtual address for these registers is
0xB000 0000 through 0xB0FF FFFF.
Figure 3.1 LR4500 Master/Slave Memory Map
0x0000 0000
0x0400 0000
0x1000 0000
0xFFFF FFFF
Lbus Access Area
Internal Register Area
LR4500 Master Address Map
0x1100 0000
LR4500 Slave Address Map
0x0000 0000
0x0400 0000
0x1000 0000
0xFFFF FFFF
Lbus Access Area
Unusable Area
0x1100 0000
Lowest Order
Address
Highest Order
Address
Reserved Main Memory Area
Reserved Main Memory Area
DRAM Main Memory Area
DRAM Main Memory Area
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