參數(shù)資料
型號： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述： 超標(biāo)量微處理器（超標(biāo)量微處理器）
文件頁數(shù)： 89/172頁
文件大小： 1142K
代理商： LR4500
Internal Interface
5-19
SLAoEn
Address Output Enable
Output from SCLC
to DRAMC
The SCLC asserts this signal to indicate that the address
bus lines, SCAp[31:0], are valid. The signal remains
active throughout the bus transaction. SCAoEn also
enables SCTBSTn, SCTBEn, and SCTPWn. This signal
is not valid at the same time as SCAoEn, which is the
Address Output Enable signal output from the CW4011
shell to the SCLC described on
page 5-14
.
SLWRn
SCLC Write Enable
The SCLC asserts this signal throughout a DRAM write
operation and outputs it to the DRAMC. It performs the
same function for a CW4011 write transaction to DRAM
that SCDoEn (
page 5-17
) performs for an SCLC write
transaction to DRAM.
Output from SCLC to DRAMC
5.2.2 External Buffering for SCbus Signals
You must provide external buffering for certain SCbus signals, including:
Address bus SCAp[31:0]
Address output enable signals SCAoEn and SLAoEN
SC data bus SCDp[63:0]
Data output enable SCDoEn
SCbus byte enable SCBEn[7:0]
Figure 5.5
shows an example of a buffer configuration in which the
bidirectional address bus is buffered at the SCLC and CW4011 ends by
BTS4A*32
3-state buffers. When the CW4011 asserts SCAoEn, the signal
enables the buffer at the CW4011 end. When the SCLC asserts SLAoEn,
the signal enables the buffer at the SCLC end.
During device scan test, CW4011 buffers should drive the bus. When
TESTMp is asserted the output enable signal, SCAoEn, is asserted.
Other address output enable signals must be deasserted.
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