參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 137/172頁
文件大?。?/td> 1142K
代理商: LR4500
ICEport Signals
9-5
9.4 ICEport Signals
This section describes the signals that comprise the bit-level interface of
the ICEport. The following paragraphs outline the conventions used in
the signal descriptions:
The signals are described in alphabetical order by mnemonic within
each functional group. Each signal definition contains the mnemonic
and the full signal name.
The mnemonics for signals that are active HIGH, or for clock signals
with a positive rising edge, end with a “p;” signals that are active
LOW end with “n.”
The term assert means to drive TRUE or active; deassert means to
drive FALSE or inactive.
Input and Output in the signal headings refer to I/Os with respect to
the ICEport, not with the core. For example, SCTSSn is a core
output, but it is considered an ICEport input and therefore is labeled
“Input.”
All input signals, except for ICERXp and ICECLKp, are read on the
positive edge of SCLKp and must therefore be generated
synchronously with SCLKp.
All output signals (except ICETXp) are also generated synchronously
at the rising edge of the SCLKp clock. The ICETXp signal is
synchronous to the rising edge of ICECLKp, except during a reset
where ICETXp is asserted asynchronously to ICECLKp.
In normal serial send and receive operations through the ICEport,
ICECLKp runs at 16 times the rate of serial bit transmission/receive.
This allows ICECLKp to define the bit width for each UART serial bit.
The ICEport assumes that each serial bit for both receive and
transmit is 16 x ICECLKp, or 16 ICECLKp cycles.
Table 9.1
summarizes the ICEport signals. Detailed descriptions follow
the table. Note that the SCbus master can either be the SCLC module
or the CW4011 processor. External logic refers to logic not related to the
CW4011 core, the SCLC, or the ICEport.
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