參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 107/172頁
文件大?。?/td> 1142K
代理商: LR4500
DRAM Refresh
6-13
When the system is initialized, the DRAM Controller writes the Refresh
Interval Time data into the Refresh Register. The same data is stored in
the Refresh Counter as the Refresh Counter Value. The DRAM Controller
reads the contents of both registers only during testing.
Figure 6.5 DRAM Refresh Interval Timer
After a cold reset, the counter stops counting. Once the DRAM Controller
has written the value for the Refresh Interval Time into the Refresh
Register, the counter loads the same initial value and starts counting by
decrementing the initial value by 1 at each clock input. When the counter
has counted down to 1, the DRAM Controller sets the REF bit in the
LR4500 Configuration and Cache Control Register (
page 3-5
),
requesting a refresh command. The initial value is then reloaded and the
process starts again. Note that the counter never counts down to 0. If a
DRAM transaction is proceeding when the DRAM Controller issues the
refresh command, the status of the refresh command is ‘pending,’ and a
refresh command cycle is generated when the preceding transaction has
been completed. Only a cold reset can stop the refresh counter.
The setting of the Refresh Register is derived from the DRAM clock cycle
value, the required refresh interval (15,625 ns), and the CAS latency (CL)
setting. The CL setting determines the number of clock cycles required
before data is available.
Table 6.4
lists Refresh Register programming
values for four operating frequencies. You can calculate value A by
dividing the refresh interval by the microprocessor’s clock cycle time. You
can calculate the value programmed into the Refresh Register by
subtracting the number of clock cycles required for the longest
transaction, which is a burst read transaction (B), from the value A. In
the first example shown, the Refresh Register should be set to 1551
(0x61A).
Refresh Register
(write)
31
11 10
0
Reserved (0)
Refresh Interval Time
Refresh Counter
(read)
31
11 10
0
Reserved (0)
Refresh Counter Value
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