參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 142/172頁
文件大?。?/td> 1142K
代理商: LR4500
9-10
ICEport
All register read transactions return zeros for bits [31:8], and data for bits
[7:0]. For read transactions, the register bits are mapped with SCDip[31]
to sc_ICEDop[31], and so on. For write transactions, the register bits are
mapped with SCDop[7] to sc_ICEDip[7], and so on. During write
transactions, data on SCDop[31:8] is ignored, write transactions to read-
only registers are ignored, and read transactions from write-only
registers return undefined data.
All registers must be accessed using word accesses only, to avoid
conflict between big-endian and little-endian data structures, and to avoid
partial update problems.
Table 9.2 ICEport Register Addresses
Physical Address
Virtual Address
Access
Register
0x10FF0000
1
1. The physical address for the Rx Status Register is the same as the physical
address for the Rx Setup Register. Similarly, the virtual addresses are the
same. The Rx Status Register is a read register and the Rx Setup Register
is a write register. This means that when the addresses are accessed, the
register accessed depends on the condition of the read/write signal.
0xB0FF0000
1
Read
Rx Status Register
0x10FF0000
1
0xB0FF0000
1
Write
Rx Setup Register
0x10FF0004
0xB0FF0004
Read
Rx Data Register
0x10FF0008
0xB0FF0008
Read
Tx Status Register
0x10FF000C
0xB0FF000C
Write
Tx Data Register
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