參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 123/172頁
文件大?。?/td> 1142K
代理商: LR4500
LR4500 as Slave on the Lbus
7-5
In the examples shown in Figures
7.1
and
7.2
, the CW4011 initiates a
SCbus transaction at T1. The SCLC module, which is part of the
LR4500, checks the phase LCLKp clock. At T4 and T5, the SCLC
asserts address strobe, LADSn. During a write transaction, the SCLC
must output data on the Lbus on the rising edge of LCLKp. The Lbus
transaction starts at T4. At T12, the SCLC samples the LRDYn signal on
the rising edge of LCLKp. The SCLC asserts the SCbus data ready
signal, SCBRDYn, at T13. At the same time it asserts the bus sizing
request signal, SCB32n. During a read transaction, the SCLC samples
data on the Lbus when it samples LRDYn. If the transaction is a write
transaction, the CW4011 places data on the SCbus at T13.
7.3 LR4500 as Slave on the Lbus
LR4500 functions as a slave on the Lbus when an Lbus device, such as
a SONIC Ethernet Controller, initiates a bus transaction. The Lbus device
accesses the system DRAM through the DRAM Controller, which is part
of the LR4500 and the LR4500 acts as a slave memory controller. The
address being accessed must fall in the range 0x 0000 0000 through
0x 03FF FFFF. The LR4500 does not assert the data ready signal for the
address range 0x 0400 0000 through 0x FFFF FFFF, since the
transaction is treated as a read/write transaction between an Lbus
master and an Lbus slave.
Figure 7.3
shows the timing requirements for
an Lbus-to-SCbus read transaction.
Figure 7.4
shows the timing
requirements for an Lbus-to-SCbus write transaction.
At T1, the LR4500 samples LHoLDp on the rising edge of LCLKp. At T2,
the SCLC module, which is part of the LR4500, asserts SCbus hold
request, SCHRQn. The CW4011 asserts the SCbus hold grant signal,
SCHGTn, at T4. At T7, the SCLC module asserts the Lbus hold
acknowledge signal, LHLDAp, on the rising edge of LCLKp. While
LHLDAp is asserted, the SCLC module asserts LRDYoEn to drive
LRDYn. At T9 or later, the Lbus master starts an Lbus transaction. The
SCLC samples LADSn on the rising edge of LCLKp. If the signal is
asserted, the SCLC module knows the Lbus master has initiated an Lbus
transaction. At T12, the SCLC module decodes sampled address inputs
and starts an SCbus transaction if the address is in the DRAM area. The
DRAM Controller asserts the data ready signal, DRRDYn, when a
transaction is completed. At T17 and T18, the SCLC module asserts
LRDYn and the Lbus transaction is completed.
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