參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 128/172頁
文件大?。?/td> 1142K
代理商: LR4500
7-10
SCbus and Local I/O Bus Converter Module
If software sets the SEVI bit in the EXVI Register, the EVInt input of
LR4500 is asserted and causes an exception. External Vectored
Interrupts are enabled in the CCC Register, and interrupts are enabled
in the Status Register. The software must write the extended address to
the EVIA bit at the same time that it sets the SEVI bit.
The nonmaskable interrupt input to LR4500, NMI, can be used to cause
an external vectored interrupt, EVInt. This bit selects the function of the
NMI/EVInt pin. If the bit is cleared to 0, the pin generates a nonmaskable
interrupt (NMI). If the bit is set to 1, the pin generates an external
vectored interrupt (EVInt). The address is still supplied by the EVIA bits.
If HEVI is cleared to 0, the falling edge of NMI causes an NMI exception.
If HEVI is set to 1, the falling edge of NMI causes an EVInt exception
provided that the interrupt enable bit the Status Register is set.
A cold reset clears all bits of the EXVI Register. The EVIA[31:2] bits are
cleared when the CW4011 reads them. EVIA[31:2] must be programmed
again if they are to be used again.
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