參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 20/172頁
文件大小: 1142K
代理商: LR4500
2-4
Functional Blocks
2.1.5 Caches
The LR4500 has separate instruction and data caches—I-cache and
D-cache—that can be organized as direct-mapped or two-way set-
associative caches. The cache controllers support configurations of 1, 2,
4, or 8 Kbytes for each set. Thus, the smallest supported configuration
is a 1-Kbyte direct-mapped cache, and the largest is a 16-Kbyte two-way
set-associative cache, with 8 Kbytes per set. You can select between
Write Back and Write Through modes. You can also configure both sets
of the D-cache and one set of the I-cache for scratchpad RAM mode.
Refer to Chapter
8
, “
Cache Configuration and Maintenance
,” for more
information on this subject.
2.2 Synchronous DRAM Controller
The DRAM Controller is part of the LR4500 reference device, and it is
external to the CW4011 shell, as shown in
Figure 2.1
on
page 2-2
. It
generates DRAM transactions in response to requests from the CW4011
core or from the SCLC module. The DRAM Controller also generates
initialization cycles and refresh cycles for DRAM. Chapter
6
, “
DRAM
Controller and Memory Bus
,” provides detailed information about DRAM
and the DRAM controller.
2.3 SCbus to Local I/O Bus Converter
The SCLC module provides an interface between the internal CW4011
microprocessor bus (SCbus) and the external Local I/O bus (Lbus). The
Lbus connects such devices as boot-ROM, serial I/O devices, and the
Ethernet Controller to the LR4500.
The SCbus is a 32-bit address, 64-bit data bus. The Lbus, which is a
subset of the industrial standard VLbus, is a 32-bit address, 32-bit data
bus. The CW4011 uses the SCLC module to access devices on the
Lbus. Devices on the Lbus access the DRAM main memory through the
SCLC module and the DRAM Controller.
The CW4011 microprocessor generally has ownership of the SCbus and
the Lbus. When a device on the Lbus wants to access the DRAM, it
asserts the bus hold request signal on the Lbus. The SCLC module
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