參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 10/172頁
文件大?。?/td> 1142K
代理商: LR4500
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Preface
Chapter 4,
Instruction Set
, lists and describes the instructions that
make up the LR4500 instruction set, defines the instruction set
extensions, and describes CPU instruction opcode bit encoding.
Chapter 5,
Bus Interface Descriptions
, describes the interface
signals for the major LR4500 interfaces including the signals that
provide the external interface between the LR4500 and external
devices, and the interface signals internal to the LR4500. The
chapter also describes the buffering required for certain interface
signals.
Chapter 6,
DRAM Controller and Memory Bus
, describes the
synchronous DRAM Controller and the memory bus. It also provides
timing information for different DRAM transactions.
Chapter 7,
SCbus and Local I/O Bus Converter Module
, describes
the Lbus and explains how the LR4500 interacts with the Lbus
through the SCLC module.
Chapter 8,
Cache Configuration and Maintenance
, describes the
I-cache and D-cache configurations and explains how to maintain the
caches after power is turned on.
Chapter 9,
ICEport
, describes the ICEport building block that
provides a full-duplex serial UART (universal asynchronous receive
and transmit) port for the LR4500.
Chapter 10,
Organization of Clock and Exception Signals
,
describes the organization of the LR4500 clock signals and the
exception-handling signals.
Chapter 11,
Specifications
, defines the electrical characteristics of
the LR4500. It also provides packaging information, including the
mechanical layout of the LR4500, the chip’s dimensions, and pin
locations.
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