參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 14/172頁
文件大?。?/td> 1142K
代理商: LR4500
1-2
Introduction
The DRAM controller that provides the Memory Bus (Mbus) interface
between the LR4500 and external synchronous memory devices.
The SCbus/Lbus Converter that controls the Local I/O bus (Lbus)
and external Lbus devices
A Phase-Locked Loop (PLL) circuit that supplies clock inputs to the
other modules in the LR4500
The ICEport UART (universal asynchronous receiver/transmitter) is
used to download SerialICE application software and to debug the
LR4500.
Figure 1.1 Block Diagram of LR4500 and Evaluation Board Circuitry
Chapter 2, “
Functional Blocks
,” provides detailed information about the
functional elements of the LR4500.
The LR4500 is housed on an evaluation board (BDLR4500) that allows
you to use and test the LR4500. In addition to the LR4500, the board
contains:
The DRAM array that communicates with the LR4500 through the
Mbus.
SCbus
Interface
Cache
Invalidation
Interface
Local IO Bus
(Lbus)
Memory Bus
(Mbus)
Synchronous
DRAM
Controller
(SDRAMC)
SCbus/Lbus
Converter
(SCLC)
Synchronous
DRAM
Main Memory
Boot
ROM
Serial
I/O
Ethernet
Controller
(SONIC)
Phase-Locked
Loop (PLL)
Cell
LR4500
ICEport
(UART)
CW4011 Shell
Reference
Device
Evaluation
Board
Microprocessor
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