參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 81/172頁
文件大?。?/td> 1142K
代理商: LR4500
Internal Interface
5-11
SCANENBp
Global LR4500 Scan Enable—LSI Logic Use Only
Input
Strap this signal LOW on the board.
TESTMp
Test Mode for Scan—LSI Logic Use Only
This input is reserved for factory use during testing. Strap
it LOW on the board.
Input
ZSTATEn
Global 3-State Control—LSI Logic Use Only
This input is reserved for factory use during testing. Strap
it HIGH on the board.
Input
5.1.5 CW4011 Core Monitor Signal
The LR4500 has one pin that enables you to monitor the behavior of the
CW4011 core.
MCLKp
Internal Clock Monitor
This output from the internal clock allows you to check
the clock phase. When you are not using the pin to check
the clock, the output should be unconnected.
Output
5.2 Internal Interface
This section describes the LR4500 internal interfaces: SCbus, external
buffering required for certain SCbus signals, and the reset/interrupt
interface.
Each signal definition contains the mnemonic and the full signal name.
Active LOW signals have an ‘n’ suffix, for example, SCRESETn. Active
HIGH signals have a ‘p’ suffix, for example, MDQMp. ‘Assert’ means to
drive the signal TRUE or active. ‘Deassert’ means to drive the signal
FALSE or inactive.
5.2.1 SCbus Interface
The SCbus interface provides the link between CW4011 core elements
that are part of the CW4011 shell and the DRAMC and SCLC modules
that are external to the CW4011 shell, but are part of the LR4500
reference device.
Figure 5.4
shows a simplified view of this interface.
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