參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 141/172頁
文件大小: 1142K
代理商: LR4500
ICEport Registers
9-9
ICETXp
TX Serial Bit Transmit
This is an off-chip output that holds the UART serial
output data stream. Each transmitted bit is 16 ICECLKp
cycles long.
Output
SCLKp
System Clock
SCLKp is the global system clock input from the CW4011
core.
Input
SE
Scan Test Mode Enable
Asserting SE HIGH enables the scan chain; deasserting
SE LOW disables the scan operation. The TESTMp
signals must also be continuously asserted to enable the
entire scan test.
Input
SI
Scan Test Input
SI is the scan chain data input signal.
Input
SO
Scan Test Output
SO is the scan chain data output signal.
Output
TESTMp
Scan Test Setup
When asserted HIGH, this signal sets up the scan test,
so that scan mode is possible in the SCLKp clock
domain. TESTMp signals must be continuously asserted
to enable the scan test. The ICECLKp signal is ignored
while TESTMp is enabling the scan test mode.
Input
9.5 ICEport Registers
All ICEport registers are memory-mapped as shown in
Table 9.2.
The
default ICEport virtual base address is set to 0xB0FF 0000
(0x10FF 0000 physical address). Users can customize the ICEport
address by altering the addresses in the HDL models. However, the last
nibble (bits 0 to three) must be kept the same, since these four bits
determine which ICEport register to access. The addresses must also be
both unmapped to prevent an installed MMU from remapping memory
addresses and uncached to maintain data congruency. For these
reasons, LSI Logic suggests using unmapped and uncached memory
space kseg1.
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