參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 114/172頁
文件大?。?/td> 1142K
代理商: LR4500
6-20
DRAM Controller and Memory Bus
6.9 DRAM Transactions
Once the DRAM Controller has initialized the DRAM, it can initiate
various types of DRAM accesses. This section shows the timing require-
ments for three typical DRAM accesses:
Figure 6.7
shows the timing for a single burst read transaction.
Figure 6.8
(
page 6-22
) shows the timing for two continuous write
transactions.
Figure 6.9
(
page 6-23
) shows the timing for a burst write transaction.
In all cases, the DRAM is an 80 MHz, 10 ns device. Other timing param-
eters for this device are as follows:
CAS Latency (CL) = 3. (Refer to
page 6-6
for further information
about CL.)
Active RAS to Read/Write Command Period Cycles (RCD) = 3.
(Refer to
page 6-7
for further information about RCD.)
Refresh to Refresh/Active Command Period Cycles (RC) = 8.
(Refer to
page 6-7
for further information about RC.)
Active to Precharge Command Period (RAS) = 6.
(Refer to
page 6-8
for further information about RAS.)
Precharge to Active Command Period (RP) = 3.
(Refer to
page 6-8
for further information about RP.)
Data In to Precharge Command Period (DPL) = 2.
(Refer to
page 6-8
for further information about DPL.)
Data In to Active/Refresh Command Period (DAL) = 5.
(Refer to
page 6-8
for further information about DAL.)
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