參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 147/172頁
文件大?。?/td> 1142K
代理商: LR4500
ICEport Operations
9-15
ICEport constantly decodes SCAop[31:0] and monitors SCTSSn for
transactions that target the ICEport. If the ICEport is the target of a
transaction, it checks the SCDoEn signal to determine whether this
transaction is a read or a write transaction.
For a read transaction, the ICEport places data on the sc_ICEDop output
bus, asserts both sc_ICERDYp, and then asserts sc_ICEDoEp at the
next cycle.
For a write transaction, the ICEport latches the data on sc_ICEDip into
the proper register on the next rising edge of the clock, and asserts
sc_ICERDYp at the following clock cycle. In order to ensure that
information is not lost, the SCbus master must hold the SCAop[31:0],
SCDoEn, and SCDop[31:0] signals until the ICEport asserts the
sc_ICERDYp acknowledge signal.
For data transfer, the SCDop[7:0] output bus connects to the ICEport
sc_ICEDip[31:0] input bus. The SCDip[31:0] input bus connects to the
ICEport sc_ICEDop[31:0] output bus. The upper 32 bits of both SCbus
data buses, SCDop[63:32] and SCDip[63:32], are not used for ICEport
transactions.
Figure 9.8
shows the timing relationships for an ICEport read transaction,
and
Figure 9.9
shows the timing relationships for an ICEport write
transaction. In both examples, CRESETn, WRESETn, and TESTMp are
assumed to be deasserted throughout the transaction, and these signals
are not shown in the figures. All read/write transactions are synchronous
to the rising edge of the SCLKp. Detailed cycle descriptions follow the
figures.
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