參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 146/172頁
文件大?。?/td> 1142K
代理商: LR4500
9-14
ICEport
9.5.5 Tx Data Register
The write-only Tx Data Register, shown in
Figure 9.7
, holds the serial
transmission data.
Figure 9.7 Tx Data Register
R
Reserved Bits
These bits are reserved for LSI Logic and any write
transactions to these bits are ignored.
[31:8]
TxData
Transmitted Bit Stream
When the TxRDY bit in the Tx Status Register is set, data
that is to be transmitted through ICETXP may be written
to the TxData bits. Write transactions to the TxData bits
when TxRDY is zero are ignored.
[7:0]
9.6 ICEport Operations
This section describes the different ICEport operations, and is divided
into the following sections:
Section 9.6.1, “SCbus Read/Write Transactions” page 9-14
Section 9.6.2, “Reset” page 9-17
Section 9.6.3, “The Serial Bit Stream” page 9-18
Section 9.6.4, “ICEport Receive and Transmit” page 9-18
Section 9.6.5, “Clock Domains and Properties” page 9-21
9.6.1 SCbus Read/Write Transactions
All read or write transactions to the ICEport occur through the SCbus.
Both transactions require two cycles once SCbus arbitration is decided.
For either transaction, the bus master must first win arbitration for SCbus
control and decide to initiate a transaction. The bus master then places
the target address for the transaction on SCAop[31:0] and asserts
SCTSSn for one cycle to indicate the start of a new transaction. The
31
8
7
0
R
TxData
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