Data Sheet
June 2001
DSP16410B Digital Signal Processor
40
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.5 Memory Maps
(continued)
4.5.5 Y-Memory Maps
Figure 7. Y-Memory Maps
INTERNAL
EXTERNAL
0x00000
.
0x17FFF
0x1FFFD
CACHEn(PRIVATE
)
62 words
0x1FFC0
0x1FFFE
0x3FFFF
0x80000
.
RESERVED
0x1FFBF
YMAP
(WEROM = 0)
RESERVED
.
0x7FFFF
16 bits
EIO
(SHARED
§
)
128 Kwords
0xFFFFF
0x60000
INTERNAL I/O
(SHARED
§
)
128 Kwords
ERAM
(SHARED
§
)
TPRAMn(PRIVATE
)
96 Kwords
.
0x5FFFF
0x40000
nis 0 for CORE0 or 1 for CORE1. Private memory can be accessed by the core with which it is associated. TPRAM0, CACHE0, and IROM0
cannot be accessed directly by CORE1. TPRAM1, CACHE1, and IROM1 cannot be accessed directly by CORE0. Both TPRAM0 and
TPRAM1 can be accessed by the DMAU and PIU.
Internal I/O consists of shared local memory (SLM) and internal memory-mapped registers.
A shared memory space is accessible by both CORE0 and CORE1, and is also accessible by the DMAU and the PIU.
EROM and ERAM can each be configured as four glueless 512 Kword (1 Mbyte) segments or one 8 Mword (16 Mbytes) segment. EIO can
be configured as four glueless 128 Kword (256 Mbytes) segments or one glueless 2 Mword (4 Mbytes) segment. (See
Section 4.14.4.3
beginning on page 111
for details.)
§
0x00000
.
0x17FFF
0x1FFFD
CACHEn(PRIVATE
)
62 words
0x1FFC0
0x1FFFE
0x3FFFF
0x80000
.
0x1FFBF
YMAP
(WEROM = 1)
.
0x7FFFF
16 bits
0xFFFFF
0x60000
INTERNAL I/O
(SHARED
§
)
128 Kwords
EROM
(SHARED
§
)
TPRAMn(PRIVATE
)
96 Kwords
.
0x5FFFF
0x40000
0x18000
0x18000
EIO
(SHARED
§
)
128 Kwords
RESERVED
RESERVED