
Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
237
6 Software Architecture
(continued)
6.2 Registers
(continued)
6.2.3 Register Encodings
(continued)
Table 147. imux (Interrupt Multiplex Control) Register
15—14
XIOC[1:0]
13—12
Reserved
11—10
IMUX9[1:0]
9—8
7
6
5
4
3
2
1
0
IMUX8[1:0]
IMUX7 IMUX6 IMUX5 IMUX4 IMUX3 IMUX2 IMUX1 IMUX0
Bit
Field
Controls
Multiplexed
Interrupt
XIO
Value
Interrupt
Selected
Description
R/W Reset
Value
15—14
XIOC[1:0]
00
01
10
11
0
00
01
10
11
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (logic low)
DMINT4
DMINT5
Reserved
—
INT3
POBE
PIBF
Reserved
INT2
POBE
PIBF
Reserved
SIINT1
DDINT2
SOINT1
DSINT2
SIINT0
DDINT0
SOINT0
DSINT0
DDINT2
DDINT3
DSINT2
DSINT3
DDINT0
DDINT1
DSINT0
DSINT1
—
R/W
00
DMAU interrupt for MMT4.
DMAU interrupt for MMT5.
Reserved.
Reserved—write with zero.
Pin.
PIU output buffer empty.
PIU input buffer full.
Reserved.
Pin.
PIU output buffer empty.
PIU input buffer full.
Reserved.
SIU1 input interrupt.
DMAU destination interrupt for SWT2 (SIU1).
SIU1 output interrupt.
DMAU source interrupt for SWT2 (SIU1).
SIU0 input interrupt.
DMAU destination interrupt for SWT0 (SIU0).
SIU0 output interrupt.
DMAU source interrupt for SWT0 (SIU0).
DMAU destination interrupt for SWT2 (SIU1).
DMAU destination interrupt for SWT3 (SIU1).
DMAU source interrupt for SWT2 (SIU1).
DMAU source interrupt for SWT3 (SIU1).
DMAU destination interrupt for SWT0 (SIU0).
DMAU destination interrupt for SWT1 (SIU0).
DMAU source interrupt for SWT0 (SIU0).
DMAU source interrupt for SWT1 (SIU0).
13—12
11—10
Reserved
IMUX9[1:0]
—
R/W
R/W
0
00
MXI9
9—8
IMUX8[1:0]
MXI8
R/W
00
7
IMUX7
MXI7
R/W
0
6
IMUX6
MXI6
R/W
0
5
IMUX5
MXI5
R/W
0
4
IMUX4
MXI4
R/W
0
3
IMUX3
MXI3
R/W
0
2
IMUX2
MXI2
R/W
0
1
IMUX1
MXI1
R/W
0
0
IMUX0
MXI0
R/W
0