- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377000 > DSP16410 16-bit fixed point DSP with Flash PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP16410 |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁(yè)數(shù)： | 223/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)當(dāng)前第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)第316頁(yè)第317頁(yè)第318頁(yè)第319頁(yè)第320頁(yè)第321頁(yè)第322頁(yè)第323頁(yè)第324頁(yè)第325頁(yè)第326頁(yè)第327頁(yè)第328頁(yè)第329頁(yè)第330頁(yè)第331頁(yè)第332頁(yè)第333頁(yè)第334頁(yè)第335頁(yè)第336頁(yè)第337頁(yè)第338頁(yè)第339頁(yè)第340頁(yè)第341頁(yè)第342頁(yè)第343頁(yè)第344頁(yè)第345頁(yè)第346頁(yè)第347頁(yè)第348頁(yè)第349頁(yè)第350頁(yè)第351頁(yè)第352頁(yè)第353頁(yè)第354頁(yè)第355頁(yè)第356頁(yè)第357頁(yè)第358頁(yè)第359頁(yè)第360頁(yè)第361頁(yè)第362頁(yè)第363頁(yè)第364頁(yè)第365頁(yè)第366頁(yè)第367頁(yè)第368頁(yè)第369頁(yè)第370頁(yè)第371頁(yè)第372頁(yè)第373頁(yè)
Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
167
4 Hardware Architecture
(continued)
4.16 Serial Interface Unit (SIU)
(continued)
4.16.10 Frame Error Detection and Reporting
The SIU supports back-to-back frame processing.
However, when a frame has completed, the SIU stops
processing until the beginning of another frame is
detected by sampling a new frame sync. If the new
frame sync is detected before a frame has completed,
the following actions are taken by the SIU:
1. An interrupt request is generated, if enabled. Specif-
ically, if the occurrence of SIFS is detected before
the end of the input frame, an input error has
occurred. If enabled via the IINTSEL[1:0] field
(
SCON10
[12:11]—see
Table 111 on page 188
), the
SIINT interrupt is asserted to the DSP cores. If the
occurrence of SOFS is detected before the end of
the output frame, an output error has occurred. If
enabled via the OINTSEL[1:0] field
(
SCON10
[14:13]), the SOINT interrupt is asserted to
the cores.
2. The IFERR flag (input frame error) or OFERR flag
(output frame error) is set in the
STAT
register
(
Table 116 on page 194
), as appropriate. All sub-
frame, channel, and bit counters are reinitialized and
a new input or output frame transaction is initiated.
The data from the incomplete frame can be errone-
ous and the core software should perform error
recovery in response to the setting of IFERR or
OFERR.
3. If the SIU is in passive mode (clocks and frame sync
are externally generated) or in active mode with the
AGSYNC field (
SCON12
[14]) cleared, the new frame
transaction begins immediately after the new frame
sync is detected. If the SIU is in active mode with
AGSYNC set and an externally generated clock is
applied to SCK, the new frame transaction begins
after the detection of the first frame sync that does
not cause resynchronization of the bit clocks. See
Section 4.16.6 on page 163
for details on resynchro-
nizing bit clocks in active mode.
4.16.11 Frame Mode
Frame mode allows for a high channel capacity, but
sacrifices channel selectivity. A program selects frame
mode by setting the IFRAME field (
SCON1
[7]—
Table 102 on page 183
) for input and the OFRAME
field (
SCON2
[7]—see
Table 103 on page 184
) for
output. In this mode, the SIU processes all channels in
the frame. A maximum of 128 consecutive channels in
the frame can be accessed. The IFLIM[6:0] field
(
SCON1
[6:0]) and OFLIM[6:0] field (
SCON2
[6:0])
define the number of channels in each input and output
frame.
If using frame mode, the user performs the following
steps in software:
1. Configure the number of channels in the frame
structure (1 to 128) by programming the IFLIM[6:0]
field with the input frame size, and the OFLIM[6:0]
field with the output frame size. The input and out-
put frame size is the number of channels minus
one. For simple serial communications (one channel
per frame), these fields should be programmed to
zero.
2. Configure the channel size (4, 8, 12, or 16 bits) by
writing the ISIZE[1:0] and OSIZE[1:0] fields
(
SCON0
[4:3] and
SCON0
[12:11]—see
Table 101 on
page 182
). Select LSB-first or MSB-first by pro-
gramming the IMSB and OMSB fields (
SCON0
[2]
and
SCON0
[10]). Configure the data format by pro-
gramming the IFORMAT[1:0] and OFORMAT[1:0]
fields (
SCON0
[1:0] and
SCON0
[9:8]).
3. Program
ICIX
0—1
and
OCIX
0—1
(the 16-bit
channel index registers, see
Table 118 on page 195
)
to assign specific SIU input and output channels to
be routed to one of two DMAU SWT channels
(SWT0 or SWT1 for SIU0; SWT2 or SWT3 for
SIU1). The maximum number of channels that
ICIX
0—1
or
OCIX
0—1
can specify is 32 (two
16-bit registers). If the number of channels is
greater than 32, the DMAU routing specified for
channels 0—31 is applied to channels 32—63,
channels 64—95, etc., as shown in
Table 120 on
page 196
and
Table 119 on page 195
. For the spe-
cial case of simple serial communications (one
channel per frame), program channels 0 and 1 to the
same value, i.e., program
ICIX
0—1
[1:0] to the
same value for input and
OCIX
0—1
[1:0] to the
same value for output.
4. Enable frame mode by setting IFRAME (
SCON1
[7])
and OFRAME (
SCON2
[7]).
5. Disable channel mode by clearing the ISFIDV_E
field (
SCON3
[2]—see
Table 104 on page 185
),
ISFIDV_O field (
SCON3
[5]), OSFIDV_E field
(
SCON3
[10]), and OSFIDV_O field (
SCON3
[13]).
6. Select passive vs. active bit clocks and frame syncs
(see
Section 4.16.5 on page 158
for details).
7. Program the IINTSEL[1:0] field (
SCON10
[12:11])
OINTSEL[1:0] field (
SCON10
[14:13]) as required by
the application.
8. Begin input and output processing by clearing the
IRESET field (
SCON1
[10]) and the ORESET field
(
SCON2
[10]).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP25-16AR | Phase-leg Rectifier Diode |
| DSP25 | Phase-leg Rectifier Diode |
| DSP25-12A | Phase-leg Rectifier Diode |
| DSP25-12AT | Phase-leg Rectifier Diode |
| DSP25-16A | Phase-leg Rectifier Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP16410C | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1629 Digital Signal Processor |
| DSP16410CG | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP16410CG Digital Signal Processor |
| DSP16411 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP16411 Digital Signal Processor |
| DSP1643 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| DSP1648C | 制造商:AGERE 制造商全稱:AGERE 功能描述:Host-Based Controller V.92 Modem Chip Set |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。