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參數(shù)資料
| 型號(hào)： | DSP16410 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁(yè)數(shù)： | 318/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410 |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
262
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
8 Signal Descriptions
(continued)
8.6 PIU Interface
The host interface to the PIU consists of 29 pins.
PD[15:0]—16-Bit Bidirectional, Parallel Data Bus:
Input/output. During host data reads, the DSP16410B
drives the data contained in the PIU output data regis-
ter (
PDO
) onto this bus. During host data writes, data
driven by the host onto this bus is latched into the PIU
input data register (
PDI
). If the PIU is not selected by
the host (PCSN is high), PD[15:0] is 3-state.
PADD[3:0]—PIU 4-Bit Address and Control:
Input. The 4-bit address input that is driven by the host
to select between various PIU registers and to issue
PIU commands. Refer to
Section 4.15.5 on page 144
for details. If unused, these input pins should be tied
low.
POBE—PIU Output Buffer Empty Flag:
Output. This
status pin directly reflects the state of the PIU output
data register (
PDO
). If POBE = 0, the
PDO
register
contains data ready for the host to read. If POBE = 1,
the
PDO
register is empty and there is no data for the
host to read. The host can read the state of this pin
anytime PCSN is asserted low. The state of this pin is
also reflected in the POBE field of the
PCON
register.
PIBF—PIU Input Buffer Full Flag:
Output. This sta-
tus pin directly reflects the state of the PIU input data
register (
PDI
). If PIBF = 0,
PDI
is empty and the host
can safely write another word to the PIU. If PIBF = 1,
PDI
is full with the previous word that was written by the
host. If the host issues another write to the PIU while
PIBF = 1, the previous data in
PDI
is overwritten. The
host can read this pin anytime PCSN is asserted low.
The state of this pin is also reflected in the PIBF field
(
PCON
[1]—
Table 73 on page 133
).
PRDY—PIU Host Ready:
Output. This status pin
directly reflects the state of the previous PIU host trans-
action. It is used by the host to extend the current
access until the previous access is complete. The
active state of this pin is determined by the state of the
PRDYMD pin. The state of PRDY is valid only if the PIU
is activated, i.e., if PSTRN is asserted. (See
Section 4.15.2.1 on page 137
for a definition of
PSTRN.)
If PRDYMD = 0, PRDY is active-low. If PRDY = 0,
the previous host read or host write is complete, and
the host can continue with the current read or write
transaction. If PRDY = 1, the previous PIU read or
write is still in progress (
PDI
is still full or
PDO
is still
empty) and the host must extend the current access
until PRDY = 0.
If PRDYMD = 1, PRDY is active-high. If PRDY = 1,
the previous host read or host write is complete, and
the host can continue with the current read or write
transaction. If PRDY = 0, the previous PIU read or
write is still in progress (
PDI
is still full or
PDO
is still
empty) and the host must extend the current access
until PRDY = 1.
PINT—PIU Interrupt:
Output. Can be set by the
DSP16410B to generate a host interrupt. If a core sets
the PINT field (
PCON
[3]—
Table 73 on page 133
), the
PIU drives the PINT pin high to create a host interrupt.
After the host acknowledges the interrupt, it must clear
the PINT field (
PCON
[3]).
PRDYMD—PIU Ready Pin Mode:
Input. Determines
the active state of the PRDY pin. Refer to the PRDY pin
description above. If unused, PRDYMD should be tied
low.
PODS—PIU Output Data Strobe:
Input. Function is
dependent upon the host type (Intelor Motorola). If
unused, PODS must be tied high:
Intelmode: In this mode, PODS functions as an out-
put data strobe and must be connected to the host
active-low read data strobe. The host read transac-
tion is initiated by the assertion (low) of PCSN and
PODS. It is terminated by the deassertion (high) of
PCSN or PODS.
Motorolamode: In this mode, PODS functions as a
data strobe and must be connected to the host data
strobe. The active level of PODS (active-high or
active-low) is determined by the state of the PIDS
pin. A host read or write transaction is initiated by
the assertion of PCSN and PODS. It is terminated
by the deassertion of PCSN or PODS.
PIDS—PIU Input Data Strobe:
Input. Function is
dependent upon the host type (Intelor Motorola). If
unused, PIDS must be tied high:
Intelmode: In this mode, PIDS functions as an input
data strobe and must be connected to the host
active-low write data strobe. The host write transac-
tion is initiated by the assertion (low) of PCSN and
PIDS. It is terminated by the deassertion (high) of
PCSN or PIDS.
Motorolamode: In this mode, the state of PIDS
determines the active level of the host data strobe,
PODS. If PIDS = 0, PODS is an active-high data
strobe. If PIDS = 1, PODS is an active-low data
strobe.
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