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| 型號(hào)： | DSP16410 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁(yè)數(shù)： | 142/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410 |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
86
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit
(DMAU)
(continued)
4.13.5 Single-Word Transfer Channels (SWT)
The DMAU provides a total of four SWT channels.
SWT0 and SWT1 are dedicated to SIU0, and SWT2
and SWT3 are dedicated to SIU1. Each SWT channel
is bidirectional and can transfer data to/from either
TPRAM0, TPRAM1, or external memory as defined by
the associated channel’s source and destination
address registers (
SADD
0—3
and
DADD
0—3
).
Two SWT channels are dedicated to each SIU so that
data from a single SIU can be routed to separate mem-
ory spaces at any time. Each SIU’s
ICIX
0—1
and
OCIX
0—1
control registers define the mapping of
serial port data to one of the two SWT channels dedi-
cated to that SIU. For example, this provides a method
for routing logical channel data on a TDM bit stream
to/from either TPRAM on a time-slot basis.
If a specific SIU issues a request for service (input
buffer full or output buffer empty), an SWT channel per-
forms a
transaction
. SWT channels provide both
source and destination transfers. A
source transac-
tion
is defined as a read from DSP16410B memory
and write to an SIU output register with the update of
the appropriate DMAU registers. A
destination trans-
action
is defined as the read of an SIU input register
and write to DSP16410B memory with the update of
the appropriate DMAU registers. For a specific SWT
channel, the size and structure of the data to be trans-
ferred to/from the SIU must be the same. As an alter-
native, the source or destination transfer for a specific
channel can be disabled, allowing separate DMAU
channels to be used for the source and destination
transfers. For example, SWT0 can be used to service
SIU0 input and SWT1 for SIU0 output.
The DMAU supports address and counter hardware for
one- and two-dimensional memory accesses for each
SWT channel. The basic data structure is called an
array
, which consists of
columns
(or buffers) and
rows
(or elements). An array can be traversed in either row-
major (two-dimensional array) or column-major (one-
dimensional array) order, as defined by the DMAU con-
trol registers for that channel (
CTL
0—3
—
Table 34 on
page 73
). Each SWT channel has two dedicated inter-
rupt signals; one to represent the status of a source
transfer and another to represent the status of a desti-
nation transfer. These signals can be used to create
interrupt sources to either core. (See
Section 4.13.7
for details.)
The SIGCON[2:0] field (
CTL
0—3
[3:1]) registers
define the exact meaning associated with
both
the
source and destination transfer interrupts. See
Table 50 on page 91
for a list of DMAU interrupts and
Table 34 on page 73
for the
CTL
0—3
bit field defini-
tions.
The following steps are taken during a
source
transaction
:
1. One of the cores sets the appropriate SRUN[3:0]
field (
DMCON0
[3:0]—
Table 31 on page 70
) to ini-
tiate transfers.
2. If the SIU 16-bit output data register (
SODR
) is
empty, the SIU requests data from the DMAU. The
DMAU reads one data word over the Z-bus from the
appropriate DSP16410B memory location using the
SWT channel’s source address register,
SADD
0—3
.
3. The DMAU transfers the data word to the corre-
sponding
SODR
register
over the peripheral data
bus, DDO.
4. The DMAU updates the SWT channel’s source
address register,
SADD
0—3
, and the source
counter register,
SCNT
0—3
.
5. The DMAU can generate a core interrupt, based on
the value of the SIGCON[2:0] field (
CTL
0—3
[3:1]).
6. If this is not the last location of the source array
(
SCNT
0—3
≠
LIM
0—3
), the DMAU returns to
step 2. If this is the last location of the source array:
If the AUTOLOAD field (
CTL
0—3
[0]—
Table 34
on page 73
) is cleared, the DMAU clears
SCNT
0—3
, clears the corresponding
SRUN[3:0] field (
DMCON0
[3:0]—
Table 31 on
page 70
), and terminates the source transfer.
If the AUTOLOAD field is set:
—The DMAU reloads
SADD
0—3
with the value
in the source base address register,
SBAS
0—3
.
—The DMAU clears the value in the source
counter register
(
SCNT
0—3
is written with 0).
—The DMAU initiates a new source transfer with-
out core intervention.
The steps taken for a
destination transaction
are:
1. One of the cores sets the appropriate DRUN[3:0]
field (
DMCON0
[7:4]) to initiate transfers.
2. If the SIU 16-bit input data register (
SIDR
) is full, the
SIU requests that the DMAU read the data. After the
DMAU acknowledges the request, the SIU places
the contents of
SIDR
onto the data bus (DSI).
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