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參數(shù)資料
| 型號(hào)： | DSP16410 |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁(yè)數(shù)： | 108/373頁(yè) |
| 文件大小： | 5643K |
| 代理商： | DSP16410 |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
52
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.10 Timer Units (TIMER0_
0—1
and
TIMER1_
0—1
)
The DSP16410B provides two timer units for each
core—TIMER0_0 and TIMER1_0 for CORE0 and
TIMER0_1 and TIMER1_1 for CORE1. Each TIMER
provides a programmable single interval interrupt or a
programmable periodic interrupt.
Figure 13 on
page 53
is a block diagram of a TIMER that contains:
I
A 16-bit control register
timer
0,1
c
(see
Table 20
on page 54
).
I
A running count register
timer
0,1
(see
Table 21 on
page 55
) consisting of a 16-bit down counter and a
16-bit period register.
I
A prescaler that divides the internal clock (CLK) by
one of 16 programmed values in the range 2 to
65536. The prescaler output clock decrements the
timer
0,1
down counter. The programmed pres-
cale value and the value written to
timer
0,1
deter-
mine the interrupt interval or period.
By default after device reset
1
, the DSP16410B clears
timer
0,1
c
and powers up the TIMER. To save power
if the TIMER is not in use, the software can set the
PWR_DWN field (
timer
0,1
c
[6]). Until the user soft-
ware writes to
timer
0,1
c
and
timer
0,1
, the TIMER
does not operate or generate interrupts.
Note:
The software can read or write
timer
0,1
only if
the TIMER is powered up (PWR_DWN = 0).
If the software reads
timer
0,1
, the value read is the
output of the down counter. If the software writes
timer
0,1
, the TIMER loads the write value into the
down counter and into the period register simulta-
neously.
The prescaler consists of a 16-bit up counter and a
multiplexer controlled by the PRESCALE[3:0] field
(
timer
0,1
c
[3:0]). PRESCALE[3:0] contains a
value N that selects the period of the prescaler output
clock as:
N
f
CLK
where f
CLK
is the frequency of the internal clock (see
Section 4.17
).
To operate the TIMER (i.e., for the prescaler to decre-
ment the
timer
0,1
down counter), the user software
must perform the following steps.
I
Write
timer
0,1
c
to program its fields as follows:
—Write 0 to the PWR_DWN field.
—Write 0 to the RELOAD field (
timer
0,1
c
[5]) for a
single interval interrupt or write 1 to the RELOAD
field for periodic interrupts.
—Write 1 to the COUNT field (
timer
0,1
c
[4]) to
enable the prescaler output clock.
—Program the PRESCALE[3:0] field to configure
the frequency of the prescaler output clock.
I
Write a nonzero value to
timer
0,1
to enable the
down counter input clock.
The software can perform the above steps in either
order, and the TIMER starts after the second step.
If the TIMER is operating and the
timer
0,1
down
counter reaches zero, the TIMER asserts its interrupt
request pulse TIME
0,1
(see
Section 4.4
for details on
interrupts). The interval from starting the TIMER to the
occurrence of the first interrupt is the following:
timer
0,1
f
CLK
If the down counter reaches zero and RELOAD is 0,
the TIMER disables the input clock to the down
counter, causing the down counter to hold its current
value of zero. The user software can restart the
TIMER by writing a nonzero value to
timer
0,1
.
If the down counter reaches zero and RELOAD is 1, a
prescale period elapses and the TIMER reloads the
down counter from the
timer
0,1
period register.
Another prescale period elapses and the prescaler
decrements the down counter. Therefore, the subse-
quent interval between periodic interrupts is the follow-
ing:
timer
0,1
f
CLK
Software can read or write
timer
0,1
while the timer is
running. If the software writes
timer
0,1
, the TIMER
loads the write value into the down counter and period
register and initializes the prescaler by clearing the
16-bit up counter. Because the TIMER initializes the
prescaler if the software writes
timer
0,1
, the interval
from writing
timer
0,1
to decrementing the down
counter is one complete prescale period.
Clearing COUNT disables the clock to the prescaler,
causing the down counter to hold its current value and
the prescaler to retain its current state. If the TIMER
remains powered up (PWR_DWN = 0), software can
stop and restart the TIMER at any time by clearing and
setting COUNT.
1. After device reset, the DSP16410B clears the down counter of
timer
0,1
and leaves the period register of
timer
0,1
unchanged.
1
+
------------
N
1
+
------------------------------------------------
)
2
N
1
+
×
--------------------------------+
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