
Data Sheet
June 2001
DSP16410B Digital Signal Processor
104
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.14 System and External Memory Interface (SEMI)
(continued)
Table 54. Enable and Strobe Pins for the SEMI External Interface
(continued)
4.14.1 External Interface
(continued)
4.14.1.3 Enables and Strobes
(continued)
ERWN1
(negative-
assertion output)
0
The external memory is configured for 32-bit data (the ESIZE pin is high), and the SEMI is perform-
ing an external write access over the least significant half of the external data bus (ED[15:0]).
The external memory is configured for 16-bit data (the ESIZE pin is low) or the external memory is
configured for 32-bit data (the ESIZE pin is high), and the SEMI is not performing an external write
access over the least significant half of the external data bus (ED[15:0]).
The SEMI 3-states ERWN1 if it grants a request by an external device to access the external mem-
ory (see description of the EREQN pin in
Table 53 on page 102
).
The SEMI is performing an external write access over the most significant half of the external data
bus (ED[31:16]).
The SEMI is not performing an external write access over the most significant half of the external
data bus (ED[31:16]).
The SEMI 3-states ERWN0 if it grants a request by an external device to access the external mem-
ory (see description of the EREQN pin in
Table 53 on page 102
).
1
Z
ERWN0
(negative-
assertion output)
0
1
Z
Pin
Value
Description
If any memory component is configured as synchronous, ECKO must be programmed as CLK/2, i.e., the ECKO[1:0] field (
ECON1
[1:0]—
Table 60 on
page 110
) must be programmed to 0x0.
The SEMI can write the EROM component only if the WEROM field (
ECON1
[11]—see
Table 60 on page 110
) is set.