Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Systems Inc.
20
7 Electrical Characteristics and Requirements
(continued)
7.3 Power Dissipation
(continued)
7.3.2 I/O Power Dissipation
I/O power dissipation is highly dependent on operating voltage, I/O loading, and I/O signal frequency. It can be
estimated as:
V
DD2
2
where C
L
is the load capacitance, V
DD
2 is the I/O supply voltage, and f is the frequency of output signal.
Table 9 lists the estimated typical I/O power dissipation contribution for each output and I/O pin for a typical applica-
tion under specific conditions. The following conditions are assumed for all cases:
I
V
DD
2 is 3.3 V.
I
The load capacitance for each output and I/O pin is 30 pF.
For applications with values of C
L
, V
DD
2, or f that differ from those assumed for Table 9, the above formula can be
used to adjust the I/O power dissipation values in the table.
Table 9. Typical I/O Power Dissipation at 3.3 V
Internal
Peripheral
Pin(s)
Type
No. of
Pins
Signal
Frequency
(MHz)
CLK/4
CLK/4
CLK/8
CLK/4
CLK/4
CLK/12
CLK/12
CLK/12
CLK/2
1
30
1
30
30
30
8
8
8
0.03
0.03
I/O Power Dissipation (mW)
185 MHz
200 MHz
SEMI
Assumptions: the SEMI is configured for a 32-bit external data bus (the ESIZE pin is high). The contribution from the EACKN pin is
negligible.
Assumption: the pins switch from input to output at a 50% duty cycle.
§
Assumption: the corresponding core has configured these pins as outputs.
ED[31:0]
ERWN[1:0]
EA0
EA[18:1]
ESEG[3:0]
EROMN
ERAMN
EION
ECKO
IO
0
—
1
BIT[6:0]
PD[15:0]
PINT
PIBF
POBE
PRDY
SICK
0
—
1
SOCK
0
—
1
SOD
0
—
1
SIFS
0
—
1
SOFS
0
—
1
I/O
O
O
O
O
O
O
O
O
O
§
I/O
O
O
O
O
O
O
O
O
O
32
2
1
18
4
1
1
1
1
14
16
1
1
1
1
2
2
2
2
2
242
15
7.6
273
60
5.1
5.1
5.1
30.2
4.6
78.5
0.33
9.8
9.8
9.8
5.2
5.2
5.2
0.019
0.019
261
16.2
8.1
294
65.9
5.4
5.4
5.4
32
4.6
78.5
0.33
9.8
9.8
9.8
5.2
5.2
5.2
0.019
0.019
BIO
0
—
1
PIU
SIU
0
—
1
C
L
f