Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
207
6 Software Architecture
6.1 Instruction Set Quick Reference
The DSP16410B instruction set consists of both 16-bit and 32-bit wide instructions and resembles C-code.
Table 128
defines the seven types of instructions. The assembler translates a line of assembly code into the most
efficient DSP16410B instruction(s). See
Table 130 on page 215
for instruction set notation conventions.
Table 128. DSP16410B Instruction Groups
Instruction
Group
MAC
F Title
(If Applicable)
F1
TRANSFER
F1E
TRANSFER
if CON
F1E
Description
The powerful MAC instruction group is the primary group of instructions used for sig-
nal processing. Up to two data transfers can be combined with up to four parallel
DAU operations in a single MAC instruction to execute simultaneously
. The DAU
operation combinations include (but are not limited to) either a dual-MAC
operation,
an ALU operation and a BMU operation, or an ALU/ACS operation and an
ADDER/ACS operation. The F1E instructions that do not include a transfer state-
ment can execute conditionally based on the state of flags
§
.
Special functions include rounding, negation, absolute value, and fixed arithmetic left
and right shift operations. The operands are an accumulator, another DAU register,
or an accumulator and another DAU register. Some special function instructions
increment counters. Special functions execute conditionally based on the state of
flags
§
.
ALU instructions operate on two accumulators or on an accumulator and another
DAU register. Many instructions can also operate on an accumulator and an immedi-
ate data word. The ALU operations are add, subtract, logical AND, logical OR,
exclusive OR, maximum, minimum, and divide-step. Some F3E instructions include
a parallel ADDER operation. The F3E instructions can execute conditionally based
on the state of flags
§
.
Full barrel shifting, exponent computation, normalization computation, bit-field
extraction or insertion, and data shuffling between two accumulators are BMU oper-
ations that act on the accumulators. BMU operations are controlled by an accumula-
tor, an auxiliary register, or a 16-bit immediate value. The F4E instructions can
execute conditionally based on the state of flags
§
.
Data move instructions transfer data between two registers or between a register
and memory. This instruction group also supports immediate loads of registers, con-
ditional register-to-register moves, pipeline block moves, and specialized stack
operations. Pointer arithmetic instructions perform arithmetic on data pointers and
do not perform a memory access.
The control instruction group contains branch and call subroutine instructions with
either a 20-bit absolute address or a 12-bit or 16-bit PC-relative address. This group
also includes instructions to enable and disable interrupts. Some control instructions
can execute conditionally based on the state of processor flags
§
.
Cache instructions implement low-overhead loops by loading a set of up to 31
instructions into cache memory and repetitively executing them as many as 2
16
– 1
times.
Executes in one instruction cycle in most cases.
A dual-MAC operation consists of two multiplies and an add or subtract operation by the ALU, an add or subtract operation by the ADDER, or
both.
§ See
Section 6.1.1
for a description of processor flags.
Special
Function
if CON
F2
ifc CON F2
if CON
F2E
ifc CON
F2E
ALU
F3
if CON
F3E
BMU
F4
if CON
F4E
Data Move
and
Pointer
Arithmetic
—
Control
—
Cache
—